A method of detecting a failure by building in a built-in self test circuit (hereinafter abbreviated as a BIST circuit) and a memory device built in a semiconductor device and using the BIST circuit in a manufacture/shipment test is usually conducted. The BIST circuit includes different types of circuits depending on the method of detecting a failure. For example, a comparator type BIST circuit configured to discriminate presence of a failure by comparing written data and read data and a compressor type BIST circuit in which a read-out result is compressed in the BIST circuit and presence of a failure is discriminated on the basis of the compressed result can be cited.
However, a memory BIST circuit represented by the comparator type BIST circuit and the compressor type BIST circuit needs to configure various functions for realizing the self test (a data generating function, an address generating function, a control signal generating function, a result analyzing function, for example) in a device as a logical circuit. There is a problem that a circuit scale increases since these logical circuits are implemented. Particularly, if a total bit amount of the memory device is relatively small, if the number of targeted memory circuits is small as one or two, or if a scale of a logical circuit portion other than the memory device is small, the scale increase of the entire semiconductor device with addition of the BIST circuit becomes a non-negligibly large ratio.
In order to reduce the increase in the circuit scale caused by addition of the BIST circuit, test contents and the analyzing function need to be reduced. However, it is likely that such reduction might damage important functions involved in a quality of the manufacture/shipment test, which is not realistic.